COMMITS
/ riscv/encoding.h November 27, 2017
A
Rename badaddr to tval
Andrew Waterman committed
A
Rename sptbr to satp
Andrew Waterman committed
May 5, 2017
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UXL=SXL=MXL
Andrew Waterman committed
April 25, 2017
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FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
Andrew Waterman committed
A
Remove hret instruction
Andrew Waterman committed
April 1, 2017
Y
update encoding.h to get PMP updates
Yunsup Lee committed
March 27, 2017
A
Separate page faults from physical memory access exceptions
Andrew Waterman committed
March 23, 2017
A
Require little-endian host
Andrew Waterman committed
March 22, 2017
W
riscv: replace rtc device with a real clint implementation
Wesley W. Terpstra committed
March 21, 2017
W
riscv: remove dependency on num_cores
Wesley W. Terpstra committed
March 20, 2017
A
PUM -> SUM; expose MXR to S-mode
Andrew Waterman committed
March 16, 2017
A
Simplify interrupt-stack discipline
Andrew Waterman committed
March 13, 2017
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Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
Andrew Waterman committed
February 27, 2017
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Sv57 and Sv64 are not spec'd yet
Andrew Waterman committed
February 25, 2017
A
New counter enable scheme
Andrew Waterman committed
February 18, 2017
A
Spike uarch needs TLB flush after SPTBR write
Andrew Waterman committed
February 15, 2017
A
sfence.vm -> sfence.vma
Andrew Waterman committed
February 8, 2017
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Encode VM type in sptbr, not mstatus
Andrew Waterman committed
August 27, 2016
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Add (degenerate) performance counter facility
Andrew Waterman committed
July 6, 2016
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Update to new PTE format
Andrew Waterman committed
June 18, 2016
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Merge sasid into sptbr
Andrew Waterman committed
June 9, 2016
A
Add degenerate HW breakpoint implementation
Andrew Waterman committed
June 3, 2016
T
Keep DCSR_XDEBUGVER unsigned.
Tim Newsome committed
May 24, 2016
T
New encoding.h for new CSR addresses.
Tim Newsome committed
May 23, 2016
T
Change DCSR bits to match spec.
Tim Newsome committed
May 9, 2016
T
Remove dependency on include file in my homedir.
Tim Newsome committed
May 4, 2016
T
Software breakpoints sort of work.
Tim Newsome committed
May 3, 2016
T
Remove unused code.
Tim Newsome committed
May 22, 2016
A
Allow delegation of device interrupts
Andrew Waterman committed
May 2, 2016
A
Remove MIPI; mip.MSIP bit is read-only
Andrew Waterman committed
May 1, 2016
A
Remove SCRs; add padding after config string
Andrew Waterman committed
April 29, 2016
A
Move much closer to new platform-M memory map
Andrew Waterman committed
April 28, 2016
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Remove MTIME[CMP]; add RTC device
Andrew Waterman committed
April 20, 2016
A
Split ERET into URET, SRET, HRET, MRET
Andrew Waterman committed
April 6, 2016
A
Remove non-standard uarch CSRs
Andrew Waterman committed
March 4, 2016
A
Fix up interrupt delegation
Andrew Waterman committed
March 1, 2016
A
Add counter-enable registers
Andrew Waterman committed
February 29, 2016
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WIP on priv spec v1.9
Andrew Waterman committed
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New definitions of misa/marchid/mvendorid
Andrew Waterman committed
February 19, 2016
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implement PUM functionality
Andrew Waterman committed
February 12, 2016
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Use simpler MTVEC scheme
Andrew Waterman committed
February 6, 2016
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WIP on priv spec v1.9
Andrew Waterman committed
November 13, 2015
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Generate device tree for target machine
Andrew Waterman committed
October 20, 2015
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Update to hopefully final RVC 1.9 encoding
Andrew Waterman committed
October 6, 2015
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RVC encoding tweak
Andrew Waterman committed
A
more work towards RVC 1.8
Andrew Waterman committed
October 2, 2015
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work towards rvc 1.8
Andrew Waterman committed
September 8, 2015
A
Improve instruction fetch
Andrew Waterman committed
September 4, 2015
A
Move towards RVC v1.8
Andrew Waterman committed