| | .github | | |
| | constraints | | |
| | fpga | | |
| | hello_world | | |
| | include | | |
| | lib | | |
| | litedram | | |
| | liteeth | | |
| | litesdcard | | |
| | media | | |
| | micropython | | |
| | openocd | | |
| | rust_lib_demo | | |
| | scripts | | |
| | sim-unisim | | |
| | tests | | |
| | uart16550 | | |
| | verilator | | |
| | .gitignore | | 263 B |
| | bitsort.vhdl | | 5.0 KB |
| | cache_ram.vhdl | | 2.7 KB |
| | common.vhdl | | 39.2 KB |
| | control.vhdl | | 11.9 KB |
| | core_debug.vhdl | | 18.3 KB |
| | core_dram_tb.vhdl | | 4.7 KB |
| | core_flash_tb.vhdl | | 2.6 KB |
| | core_tb.vhdl | | 943 B |
| | core.vhdl | | 18.5 KB |
| | countbits_tb.vhdl | | 3.9 KB |
| | countbits.vhdl | | 4.8 KB |
| | cr_file.vhdl | | 3.7 KB |
| | crhelpers.vhdl | | 1.5 KB |
| | dcache_tb.vhdl | | 7.3 KB |
| | dcache.vhdl | | 77.4 KB |
| | decode_types.vhdl | | 28.8 KB |
| | decode1.vhdl | | 80.6 KB |
| | decode2.vhdl | | 28.2 KB |
| | divider_tb.vhdl | | 22.7 KB |
| | divider.vhdl | | 4.7 KB |
| | dmi_dtm_dummy.vhdl | | 757 B |
| | dmi_dtm_ecp5.vhdl | | 9.2 KB |
| | dmi_dtm_tb.vhdl | | 7.5 KB |
| | dmi_dtm_xilinx.vhdl | | 9.7 KB |
| | dram_tb.vhdl | | 10.3 KB |
| | execute1.vhdl | | 86.9 KB |
| | fetch1.vhdl | | 16.6 KB |
| | foreign_random.vhdl | | 643 B |
| | fpu.vhdl | | 156.3 KB |
| | git.vhdl.in | | 202 B |
| | glibc_random_helpers.vhdl | | 532 B |
| | glibc_random.vhdl | | 1.2 KB |
| | gpio.vhdl | | 6.8 KB |
| | helpers.vhdl | | 10.0 KB |
| | icache_tb.vhdl | | 4.2 KB |
| | icache_test.bin | | 1024 B |
| | icache.vhdl | | 32.9 KB |
| | insn_helpers.vhdl | | 9.2 KB |
| | LICENSE | | 469 B |
| | loadstore1.vhdl | | 51.9 KB |
| | logical.vhdl | | 6.6 KB |
| | Makefile | | 12.1 KB |
| | microwatt.core | | 15.2 KB |
| | mmu.vhdl | | 63.0 KB |
| | multiply_tb.vhdl | | 8.8 KB |
| | multiply-32s.vhdl | | 1.5 KB |
| | multiply.vhdl | | 3.0 KB |
| | nonrandom.vhdl | | 437 B |
| | plru_tb.vhdl | | 2.9 KB |
| | plrufn.vhdl | | 2.1 KB |
| | pmu.vhdl | | 14.1 KB |
| | ppc_fx_insns.vhdl | | 38.2 KB |
| | predecode.vhdl | | 30.0 KB |
| | random.vhdl | | 679 B |
| | README.md | | 5.5 KB |
| | register_file.vhdl | | 7.3 KB |
| | rotator_tb.vhdl | | 11.6 KB |
| | rotator.vhdl | | 6.6 KB |
| | run.py | | 1.2 KB |
| | sim_16550_uart.vhdl | | 14.6 KB |
| | sim_bram_helpers_c.c | | 3.7 KB |
| | sim_bram_helpers.vhdl | | 1.4 KB |
| | sim_bram.vhdl | | 2.2 KB |
| | sim_console_c.c | | 1.6 KB |
| | sim_console.vhdl | | 1.1 KB |
| | sim_jtag_socket_c.c | | 3.5 KB |
| | sim_jtag_socket.vhdl | | 1019 B |
| | sim_jtag.vhdl | | 2.6 KB |
| | sim_no_flash.vhdl | | 868 B |
| | sim_pp_uart.vhdl | | 4.1 KB |
| | sim_vhpi_c.c | | 1.2 KB |
| | sim_vhpi_c.h | | 273 B |
| | soc.vhdl | | 41.2 KB |
| | spi_flash_ctrl.vhdl | | 23.4 KB |
| | spi_rxtx.vhdl | | 12.3 KB |
| | sync_fifo.vhdl | | 4.4 KB |
| | syscon.vhdl | | 11.7 KB |
| | utils.vhdl | | 1.2 KB |
| | wishbone_arbiter.vhdl | | 1.9 KB |
| | wishbone_bram_tb.bin | | 16 B |
| | wishbone_bram_tb.vhdl | | 5.0 KB |
| | wishbone_bram_wrapper.vhdl | | 2.0 KB |
| | wishbone_debug_master.vhdl | | 6.4 KB |
| | wishbone_types.vhdl | | 3.1 KB |
| | writeback.vhdl | | 7.1 KB |
| | xics.vhdl | | 17.6 KB |
| | xilinx-mult-32s.vhdl | | 8.2 KB |
| | xilinx-mult.vhdl | | 30.2 KB |
